Compact active pixel with low-noise image formation

ABSTRACT

A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only three transistors of identical polarity, in conjunction with ancillary circuits located on an imager&#39;s periphery. The use of only three transistors with a tapered reset signal allows the optical area to be increased, while still providing a low-noise imager.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to electronic imaging devicesand, more particularly, to low noise CMOS image sensors having increasedoptical area within each pixel.

2. Description of the Related Art

Significant advances in photosensor image processing for camera andvideo systems are now possible through the emergence of CMOS pixelsensors. CMOS-based imaging sensors have distinct manufacturing costsavings and consume much less power than other technologies such ascharge coupled devices (CCD). A CMOS image sensor's performance,however, is often limited by the noise generated by resetting each ofits photodiodes to a known potential after each electronic image, orpicture, is read out. Such noise is readily suppressed in CCD-basedcameras because CCD reset noise is generated on only one capacitance,i.e., the sense diffusion diode that converts the photo-generated chargeto a voltage. Also, full-frame memory is not needed to post-process thevideo to remove the reset noise because each pixel's reset and signallevels are successively read and the reset noise is conveniently removedby using only one memory element.

Similarly, the reset noise (kTC) in a CMOS sensor causes uncertaintyabout the voltage on each photodetector following the reset, but eachpixel's reset signal is not normally available. Because the reset noiseof CMOS imagers is often the dominant source of temporal noise and iscritical to overall imager performance, there is a need for apixel-based preamplifier that suppresses reset noise without requiringseparate readout of all the reset and signal levels, in order tosubsequently subtract the correlated reset noise using full-framememory. In addition, the preamplifier must be as compact as possible tomaximize the fraction of pixel area that is used for collecting thelight. Simultaneously maximizing the light-gathering area and minimizingthe reset noise maximizes sensor performance so that it can operate withusable fidelity even at low levels of light.

Mendis et al., discloses a single-stage, charge coupled device (CCD)type of image sensor in an article entitled, “A 128×128 CMOS ActivePixel Image Sensor for Highly Integrated Imaging Systems”, IEEE ElectronDevices Meeting, p. 583, 1993. The overall imager is customarilyconsidered a CMOS imager due to the co-integration of ancillary CMOSelectronics that support the pixel preamplifier—even though the schemerequires process enhancements that significantly depart fromconventional CMOS technologies. For example, the photogate must beoptically transparent in the visible part of the electromagneticspectrum. A transparent gate electrode must preferably be used toprovide reasonable sensitivity in the blue part of the visible spectrumas is commonly done in CCDs, e.g. a thin indium tin oxide (ITO) gateelectrode (e.g. U.S. Pat. No. 6,001,668). No CMOS foundry processessupport integration of ITO electrodes due to possible wafercontamination and concomitant yield loss. Nevertheless, Mendis'charge-based preamplifier ideally provides a storage site at each pixelthat readily facilitates both snapshot image formation and in-pixelcorrelated double sampling. Another key issue related to incompatibilitywith standard CMOS technology is the difficulty in optically isolatingthis storage site to eliminate image smear.

U.S. Pat. No. 5,898,168 teaches a compact CMOS pixel-based preamplifierthat uses only three transistors, reproduced as FIG. 1, by providing arow-based circuit and method for successively reading the reset andsignal levels. The system requires that the column buffer supportingeach column of pixels preferably dwells on each specific row (c.f.,FIGS. 5 and 6 of U.S. Pat. No. 5,898,168) in order to optimally performthe correlated double sampling required for suppressing reset noise bysuccessively reading each video line's reset and signal levels.Alternatively, a full page of memory must be allocated either on-chip orin the external camera electronics to subtract each pixel's reset valuefrom its final signal value on a frame-by-frame basis. Further, theimage formation process should preferably be performed on a row-by-rowbasis in order to minimize inaccuracy in measuring the reset and signallevels for each pixel. The basic three transistor circuit thus generateslarge motion artifacts because of the need to successively read thereset and signal levels during each line of video. Minimizing suchartifacts results in an alternative embodiment comprising fivetransistors per pixel, as illustrated in FIG. 1S of the '168 patent.

FIG. 2 is reproduction of the timing diagram for operating the threetransistor pixel of the '168 patent. Each line of video in the imager isseparately reset (47), signals are separately integrated (39, 41 and43), separately read (49), and then reset again to prepare for the nextframe time. An imager comprising N rows thus forms an electronic imageover N separate integration times.

In view of the foregoing, it would be desirable to have a pixel cellcomprising only three transistors, to maximize the optical area, whilestill having low-noise and minimizing motion artifacts.

SUMMARY OF THE INVENTION

In general, the present invention comprises a low-noise imaging systemfor implementation in CMOS or in other semiconductor fabricationtechnologies. The low-noise amplifier system efficiently suppressesreset (kTC) noise by using a compact preamplifier consisting of aphotodetector and only three transistors of identical polarity inconjunction with ancillary circuits located on the CMOS imager'speriphery. A tapered reset signal is applied to a reset transistorwithin the pixel to reduce the reset noise. The supporting circuits helpthe simplified pixel circuit to read the signal with low noise withouthaving to perform correlated double sampling on either successive rowsor the entire array.

The low noise amplifier system of the present invention is formed by theaggregate circuitry in each pixel, the supporting circuitry in thecolumn buffer amplifier and the row-based clock driver, and the waveformgeneration circuits servicing each column and row of pixels. The videofrom the active pixels is read out by the low-noise signal amplificationsystem in a manner that essentially eliminates the reset noise. Inaddition to means for suppressing the detector's reset noise, the columnbuffer in the downstream electronics typically performs additionalsignal processing, sample-and-hold, optional video pipelining, andcolumn amplifier offset cancellation functions to suppress the temporaland spatial noise that could otherwise be generated by the columnbuffer.

The low-noise system provides the following key functions: (1)suppresses reset noise without having to provide means for analog memoryto facilitate correlated double sampling; (2) provides high sensitivityvia source follower amplification with small sense capacitance; (3)minimizes demand on amplifier bandwidth to avoid generation of fixedpattern noise due to variations in amplifier time constant and straycapacitance; (4) provides adequate power supply rejection to enabledevelopment of imaging systems-on-a-chip that do not require elaboratesupport electronics; and (5) is compatible with application to imagingarrays having pixel pitch to below 2.7 microns with high optical fillfactor and low noise using 0.18 μm CMOS technology.

The invention has the advantage of full process compatibility withstandard silicided submicron CMOS; helps to maximize yield and minimizedie cost because the circuit complexity is distributed amongst theactive-pixels and peripheral circuits; and exploits the signalprocessing capability inherent to CMOS. Also, the spectral response isbroad from the near-ultraviolet (400 nm) to the near-IR (>800 nm).

Because the present invention has only three MOSFETs in each pixel, theinvention provides as-drawn optical fill factor of 60% at 5 μm pixelpitch using 0.25 μm design rules in CMOS. The actual optical fill factoris somewhat larger due to lateral collection and the large diffusionlength of commercial CMOS processes. A final advantage is theflexibility to collocate digital logic and signal-processing circuitsdue its high immunity to electromagnetic interference.

When fully implemented in the desired camera-on-a-chip architecture, thelow-noise APS can provide temporal read noise below 10 e− (at data ratescompatible with either video imaging or still photography via electronicmeans), fixed pattern noise significantly below 0.02% of the maximumsignal (on a par with competing CCD imagers), <0.5% nonlinearity, >1Vsignal swing for 3.3 V power supply, large charge-handling capacity, andvariable sensitivity using simple serial interface updated on aframe-by-frame basis via digital interface to a host microprocessor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings,wherein like reference numerals designate like structural elements, andin which:

FIG. 1 is a schematic of a prior art circuit taught by U.S. Pat. No.5,898,168;

FIG. 2 is a timing diagram illustrating the operation of the prior artcircuit taught by U.S. Pat. No. 5,898,168, including the specific readout of both the reset and signal levels on a row-by-row basis;

FIG. 3 is a schematic circuit diagram illustrating the compact amplifiersystem for the CMOS imaging array of the present invention;

FIG. 4 is a schematic circuit diagram illustrating the compact amplifiersystem for the CMOS imaging array of the present invention as each rowof the imaging array is being reset;

FIG. 5 is a schematic circuit diagram illustrating the compact amplifiersystem for the CMOS imaging array of the present invention duringintegration of the photo-generated signal;

FIG. 6 is a schematic circuit diagram illustrating the compact amplifiersystem for the CMOS imaging array of the present invention duringrow-based readout of the imaging array;

FIG. 7 is a small-signal equivalent circuit diagram illustrating thecompact amplifier system for the CMOS imaging array of the presentinvention during feedback-enhanced reset;

FIG. 8 is a diagram illustrating the tapered reset waveform, V_(reset),which is supplied to the Φ_(rst) clock during row-based reset of theimaging array; and

FIG. 9 is a clock timing diagram illustrating the process of signalintegration across a representative imager array and the successiveapplication row-based tapered reset.

DETAILED DESCRIPTION OF THE INVENTION

The following description is provided to enable any person skilled inthe art to make and use the invention and sets forth the best modescontemplated by the inventor for carrying out the invention. Variousmodifications, however, will remain readily apparent to those skilled inthe art, since the basic principles of the present invention have beendefined herein specifically to provide a low noise CMOS image sensorcircuit. Any and all such modifications, equivalents and alternativesare intended to fall within the spirit and scope of the presentinvention.

The CMOS readout and amplification system of the present inventionincludes an exemplary design for an active-pixel CMOS imager. Aprototype embodiment of the low-noise Active Pixel Sensor (APS)invention can be configured, for example, as a visible imager comprisingan array of 1024 (columns) by 728 (rows) of visible light detectors(photodetectors). The rows and columns of active-pixels can be spaced 5microns center-to-center using 0.25 μm design rules to provide as-drawnoptical fill factor of ˜60%. Several columns and rows of detectors atthe perimeter of the light-sensitive region are normally covered withmetal and used to establish the dark level for on-chip or off-chipsignal processing. In addition, the detectors in each row can be coveredwith color filters to produce color imagers. For example, the odd rowsmay begin at the left with red, green, then blue filters, and the evenrows may begin with blue, red, then green filters, with these patternsrepeating to fill the respective rows. A standard Bayer filter patterncan also be applied.

The low-noise amplifier system 10 of the present invention isillustrated in the schematic diagram of FIG. 3. In the preferredembodiment, each pixel 10 of the sensor array comprises a photodetector12 along with three transistors of identical polarity to efficiently usethe available pixel real estate. Transistor M1 serves dual roles as thedriver of a source follower amplifier for the specific time when thesignal is being read on a row-by-row basis, and as the driver of a resetamplifier when the photodetector 12 is being reset. Reset is alsoperformed on a row-by-row basis. Approximately 30 μs is required toreset each row of pixels via the present invention by using circuitryoutside of the pixel to effect reset amplification during signal reset.The present invention thus suppresses reset noise without having toimplement correlated double sampling using either on-chip or off-chipmemory.

Transistor M2 transfers the signal from each detector 12 to the gate oftransistor M1 and also connects the detector 12 to the reset node at thegate of transistor M1. Transistor M3 is used in two operating modes.During reset, it completes the reset loop consisting of transistor M3 inthe pixel 10, column bus 20, the reset transistor M201 in column circuit200, and column bus 22. This feedback loop discharges any charge left onthe photodetector 12 along with the charge stored on the gate oftransistor M1. In combination with amplifier transistor M1, switchtransistor M202 in column buffer 200, switch transistor M102 in columnbuffer 100, and current source I_(reset) in column buffer 200, low-noisereset of the pixel is accomplished via the aggregate reset amplifier.

The photodiode 12 may comprise a substrate diode, for example, with thesilicide cleared. In this embodiment, it is necessary to clear thesilicide because it is opaque to visible light. Pixel 10 is designed toobtain the largest available light detecting area while providing broadspectral response, control of blooming and signal integration time, andcompatibility with CMOS production processes.

For maximum compatibility with standard submicron CMOS processes,photodiode 12 may be formed at the same time as the lightly doped drain(LDD) implant of n-type MOSFETs for the chosen process; this creates ann-on-p photodiode junction in the p-type substrate that is common tomost CMOS processes. Since no additional ion implantation is necessary,the process and wafer cost for active-pixel circuit 10 are the same asthose of standard, high volume digital electronic products.

In the preferred embodiment, the photodetectors 12 are reset at thestart of image capture on a row-by-row basis as shown in FIG. 4. Bus 24connects the pixels in a specific column to a corresponding columncircuit 100. Buses 20 and 22 connect all the pixels in a specific columnto a second corresponding column circuit 200 comprising switchtransistors M201, M202 and M203, and current source I_(reset). Buses 26and 28 connect all the pixels in a specific row to corresponding rowdriver 300 consisting of clock drivers Φ_(reset), Φ_(access) and Φ_(row)_(—) _(disable). For the row being reset, Φ_(access) is “ON” and theΦ_(reset) waveform is equivalent to the V_(reset) waveform of FIG. 8.For all the other rows, both Φ_(access) and Φ_(reset) are “OFF”. Thefeedback path for resetting the photodiode 12 in a resetting row ofpixels is hence completed by connecting the drain of M3 to the drain ofM1 via the path through switch transistors transistor M201 and M202. Thephotodiode 12 is connected to the gate of M1 via switch transistor M2,which is fully enabled during this epoch. The inverter amplifierconsisting of transistor M2 and current source I_(reset) is thusconfigured as a reset integrator with capacitive-feedback provided byM1's Miller capacitance. Low-noise reset of photodiode 12 and the gateof M1 are thus performed by applying a tapered reset waveform to thegate of M3. The signal Φ_(Reset) is specifically generated in the rowdriver circuit that supports each row of the CMOS imager. Transistor Mlthus acts as a transconductance, and reset transistor M3 acts as aresistance controlled by Φ_(Reset). The series resistance of transistorM3 is gradually increased by applying slowly a decreasing ramp waveform(FIG. 8) to the gate to give the feedback transconductance of transistorM1 the opportunity to null the reset noise. This active-pixelimplementation resets within an aperture of tens of microseconds usingstandard CMOS technology.

The present invention configured for signal integration is illustratedin FIG. 5. Transistors M2 and M3 are now disabled to allow charge tointegrate on the photodiode capacitance. As photons are collected by thephotodiode 12, the resulting photocharge effectively discharges thephotodiode 12 from its previously established reset voltage. For theillustrated embodiment, the photo-generated electrons discharge theanode of photodiode 12 toward ground. All supporting row driver andcolumn buffer circuits are turned off to isolate the array of pixels forunperturbed signal integration. The pixel is configured in this mannerfor the specified integration time to provide an electronic shutter.

FIG. 6 shows the same circuitry as before, but with the switch and clockconfiguration revised for signal readout. Within each row, pixels 10 areread out from left to right or right to left. Readout is initiated byenabling switch transistor M203 so that the upper leg of M1 is connectedvia bus 22 to low-impedance voltage source V_(Read) _(—) _(amp). Thelower leg of M1 is connected to current source I_(read) in column buffer100 via column bus 24 and switch transistor M101. Transistor M1 is nowthe drive transistor of the distributed source follower so that thesignal from the gate of each transistor M1 is efficiently transferred tocolumn bus 24. Inactive rows, i.e., those not being read, are disabledby enabling transistors M3 and M301 so that the Φ_(row) _(—) _(disable)clock is connected to the gate of transistor M1 to disable the sourcefollowers in these rows.

The application of the tapered reset waveform to the composite resetamplifier enables the kTC noise envelope to decay before the resetswitch M3 is completely opened. Using tapered reset, the row isresettable to tens of microseconds for full noise suppression, orshorter time for moderate noise reduction, U.S. Pat. No. 6,697,111,entitled “COMPACT LOW-NOISE ACTIVE PIXEL SENSOR WITH PROGRESSIVE ROWRESET”, issued Feb. 24, 2004, the disclosure of which is hereinincorporated by reference, describes the generalized small-signalequivalent circuit model during reset. This circuit allows calculationof the steady-state noise envelope at the reset node depending on resetswitch resistance, R_(sw). If the reset voltage is ramped down tooslowly, too much time is needed to reset each row and operation at videoframe rates can become problematic. If the tapered-reset waveform isinstead ramped down too quickly, then the kTC noise envelope will notdecay sufficiently to suppress reset noise before the switch iscompletely opened.

In FIG. 7, which is the small-signal equivalent circuit for thecomposite reset amplifier, the photodiode node has voltage V₁ andcapacitance C₁ to ground. The amplifier output node has voltage V₂,output capacitance C_(o) and output conductance G_(o) to ground. C_(o)is the capacitance associated with the entire reset access bus, most ofwhich comes from the M3-M4 junctions of each row. g_(m) is thetransconductance of transistor M1, possibly degenerated by transistorM4; it is shown as a controlled current source. The feedbackcapacitance, C_(fb), is the parasitic Miller capacitance of transistorM1. Noise from transistor M1 is represented by current source i_(n), andnoise from transistor M3 (which is operated in the ohmic region) isrepresented by voltage source V_(n). Not included in this simplifiedmodel is the noise from capacitive feed-through of the tapered-resetwaveform.

Using the small-signal equivalent circuit, a simplified noise formulacan be derived since:

${i_{n}^{2} = {\frac{4}{3}\left( {4\mspace{14mu}{kT}} \right)g_{m}}};$v_(n)² = 4  kTR_(sw)Assuming that the amplifier's dc gain, A_(dc), is much greater than 1,then the RMS reset noise is:

$Q_{n} \cong {\sqrt{{{kT}\left( {C_{amp} + C_{sw}} \right)}_{1}} + \sqrt{{kTC}_{fb}}}$$Q_{n} \cong {\sqrt{\frac{\left( {{kT}C} \right)_{1}}{1 + k_{1} + k_{2}}} + {\sqrt{{kTC}_{fb}}\mspace{14mu}{where}}}$$k_{1} = {{\frac{R_{sw}G_{o}C_{1}}{C_{o} + C_{1}}\mspace{14mu}{and}\mspace{14mu} k_{2}} = \frac{R_{sw}g_{m}C_{fb}}{C_{o} + C_{1}}}$The tapered-clock waveform's time constant is thus appropriatelyselected so that the dimensionless quantity (k₁+k₂) is significantly >1.The reset noise is hence reduced to the much smaller quantity stemmingfrom the transconductance amplifier's feedback capacitance. In thepresent invention, this feedback capacitance is the parasitic Millercapacitance of MOSFET M1.

The present invention has the approximate design values: 1000×700format, 7 μm×7 μm pixel, g_(m)=20 μmho; G_(o)=0.08 μmho, A_(dc)=300;C₁=15 fF; C_(o)=3.0 pF and C_(fb)=0.3 fF. The desired tapered-clockfrequency of 25 kHz that is fully compatible with video rate operationhence requires R_(sw)=50 GΩ and an optimum tapered-clock time constantof 25 μs. This yields k₁+k₂=58 for the preferred embodiment, and anequivalent noise capacitance of 1.18 fF. Since the nominal detectorcapacitance is 15 fF and kTC noise is proportional to the square root ofthe relevant capacitance, the reset noise is suppressed from about 55 e−to only 14 e−.

The value of R_(sw) must be tailored to support any changes in linerate. Increasing the line rate hence requires lower switch resistance.Table 1 below numerically illustrates the impact on reset noise as thetapered-clock time constant is appropriately shortened. At a timeconstant of 2.7 μsec, the read noise degrades to 55 e−.

TABLE 1 Impact on Reset Noise for Preferred Embodiment R_(SW) (GΩ) 50 2010 5 2 1 0.5 0.1 k₁ + k₂ 58 23.2 11.6 5.8 2.32 1.16 0.58 0.12 ResetNoise (e−) 14 7 21 26 35 41 47 55 τ (μsec) 25 25 24 22 18 14 9.5 2.7In the preferred embodiment, column bus 20 is monitored by a standardcolumn buffer to read the video signal when it is available. The keyrequirements on the column buffer are similar to conventional designshaving to handle voltage-mode signals and are familiar to those skilledin the art.

In the present invention, the various clocks are generated on-chip usingstandard CMOS digital logic. This digital logic implementation thusenables “windowing,” wherein a user can read out the imager in variousformats simply by enabling the appropriate support logic to clock theappropriate sub-format. With windowing, the 1024×728 format of thecandidate embodiment can be read out as one or more arbitrarily sizedand positioned M×N arrays without having to read out the entire X×Yarray. For example, a user might desire to change a computer-compatible“VGA” format (i.e., approximately 640×480) to either Common InterfaceFormat (CIF; nominally 352×240) or Quarter Common Interface Format(QCIF; nominally 176×120) without having to read out all the pixels inthe entire array. This feature simplifies support electronics to reducecost and match the needs of the particular communication medium. As anexample, a personal teleconference link to a remote user having onlyQCIF capability could be optimized to provide QCIF resolution and thusreduce bandwidth requirements throughout the teleconference link. As afurther example, an imager configured in Common Interface Format (CIF)could provide full-CIF images while supplying windowed information forthe portions of the image having the highest interest for signalprocessing and data compression. During teleconferencing the windowaround a person's mouth (for example) could be supplied more frequentlythan the entire CIF image. This scheme would reduce bandwidthrequirements throughout the conference link.

FIG. 9 illustrates representative clock timing waveforms for reading thesignal from each row, resetting each row using a tapered reset wavefomm,and then proceeding to the next row even as signal integration continuesacross the array in the same manner as a focal plane shutter. To readthe first row, an internally generated clock waveform designated “ROW1”enables the video readout and reset processes previously shown in detailin FIGS. 4 and 6. When the corresponding “READ” pulse is high, forexample, signal readout is performed as per FIG. 6. The pixel resetconfiguration depicted in FIG. 6 occurs during the time when the TAPEREDRESET clock is shown active Oust after READ goes low). Since signalintegration and hence, image formation, proceed through the array as aprogressive, electronic focal-plane shutter per the operating specificsshown in FIG. 5, the maximum image latency between rows is one row time.The maximum image latency across the entire imaging array is about oneframe time, which is essentially about two integration times when theintegration time is comparable to the frame time. Further, sinceseparate readout of the reset and signal voltages is not needed, it isnot necessary to wait on each row to perform correlated double sampling.

Though not explicitly shown in FIG. 9, the programmability of thepresent invention also allows integration epochs of less than or equalto one line period (or time). In such a case, each line's integrationepoch does not overlap with the integration epochs of adjacent lines.The image formation, however, is still progressive and formed on arow-by-row basis without the need for reading the reset voltages.

Those skilled in the art will appreciate that various adaptations andmodifications of the just-described preferred embodiments can beconfigured without departing from the scope and spirit of the invention.Therefore, it is to be understood that, within the scope of the appendedclaims, the invention may be practiced other than as specificallydescribed herein.

1. An active pixel sensor circuit comprising: a photodetector; an accesstransistor connected to the photodetector; an electronicallyreconfigurable transistor, successively operated as a source followerdriver and a feedback amplifier, connected to an output of the accesstransistor and to a signal output bus; a reset transistor connectedbetween the access transistor and the electronically reconfigurabletransistor, wherein the reset transistor is reset with a tapered resetsignal; and a first column buffer connected to the electronicallyreconfigurable transistor and to the reset transistor, the first columnbuffer comprising: a first switch transistor connected to the resettransistor; and a second switch transistor connected to theelectronically reconfigurable transistor; wherein during a resetoperation, the first and second switch transistors connect transistorconnects the reset transistor with the electronically reconfigurabletransistor to form a feedback path.
 2. The circuit of claim 1, whereinthe transistors are MOSFETs of identical polarity.
 3. The circuit ofclaim 2, further comprising a second column buffer connected to thesignal output bus.
 4. The circuit of claim 3, further comprising a rowdisable transistor connected to the reset transistor.
 5. The circuit ofclaim 4, wherein the first column buffer, second column buffer and rowdisable transistor are connected to a plurality of active pixel sensorcircuits.
 6. The circuit of claim 5, wherein the electronicallyreconfigurable transistor operates as a driver of a source followeramplifier when a signal from the photodetector is being read out on arow-by-row basis, and operates as a driver of a reset amplifier when thephotodetector is being reset.
 7. A CMOS imager array comprising aplurality of pixels, each pixel comprising: a photodetector; an accessMOSFET having a source connected to the photodetector; an amplifierMOSFET having a gate connected to a drain of the access MOSFET, a sourceconnected to a signal bus, and a drain connected to a column buffer; areset MOSFET having a source connected to the drain of the accessMOSFET, a drain connected to the column buffer, and a gate connected toa tapered reset signal generator; and a distributed feedback amplifiercomprising the amplifier MOSFET, the reset MOSFET and the column bufferto taper reset the photodetector, wherein the column buffer comprises: afirst switch transistor connected to drain of the reset MOSFET; and asecond switch transistor connected to the drain of the amplifier MOSFET;and a reset current source connected to the second switch transistor;wherein during a reset operation, the first and second switchtransistors connect transistor connects the drain of the reset MOSFETwith the drain of the amplifier MOSFET to form a feedback path, and thesecond switch transistor connects the reset current source to theamplifier MOSFET.
 8. The imager array of claim 7, further comprising arow disable MOSFET having a source connected to the drain of the resetMOSFET and a drain connected to a row disable signal generator.
 9. Theimager array of claim 8, further comprising an access signal generatorconnected to the gate of the access MOSFET.
 10. The imager array ofclaim 9, further comprising a second column buffer connected to thesignal bus.
 11. The imager array of claim 10, wherein the MOSFETs withineach pixel are of identical polarity.
 12. The imager array of claim 11,wherein the photodetector comprises a substrate diode with the silicidecleared.
 13. An active pixel sensor circuit comprising: a photodetector;an access transistor connected to the photodetector; an amplifiertransistor, connected to an output of the access transistor and to asignal output bus; a reset transistor connected between the accesstransistor and the amplifier transistor, wherein the reset transistor isreset with a tapered reset signal; and a first column buffer connectedto the amplifier transistor and to the reset transistor, the firstcolumn buffer comprising: a first switch transistor connected to thereset transistor; and a second switch transistor connected to theamplifier transistor; and a reset current source connected to the secondswitch transistor; wherein during a reset operation, the first andsecond switch transistors connect transistor connects the resettransistor with the amplifier transistor to form a feedback path, andthe second switch transistor connects the reset current source to theamplifier transistor.
 14. An imager array circuit comprising: a firstswitch transistor connected to a first column bus; a second switchtransistor connected to a second column bus and the first switchtransistor; a reset current source connected to the second switchtransistor; a signal column bus; and a plurality of pixel circuitsconnected to the first column bus, second column bus, and signal columnbus, each pixel circuit comprising: a photodetector; an accesstransistor connected to the photodetector; an amplifier transistorconnected to the access transistor, the signal column bus and the secondswitch transistor; and a reset transistor connected to the first columnbus, the access transistor, and the amplifier transistor, wherein duringa reset operation, the first switch transistor connects the resettransistor to the amplifier transistor to form a feedback path, and thesecond switch transistor connects the reset current source to theamplifier transistor.
 15. The circuit of claim 14, wherein the amplifiertransistor operates as a driver of a source follower amplifier when asignal from the photodetector is being read out, and operates as adriver of a reset amplifier when the photodetector is being reset. 16.The circuit of claim 1, wherein the first column buffer furthercomprises: a second switch transistor connected to the electronicallyreconfigurable transistor; and a reset current source connected to thesecond switch transistor; wherein during a reset operation, the secondswitch transistor connects the reset current source to theelectronically reconfigurable transistor.